A charge-coupled device (CCD) output waveform is a sequence of pixels, where each pixel is represented as the difference between a reset level and a data level. This signal waveform is initially processed before being passed on to the automatic gain control (AGC) circuit:
The data level is subtracted from the reset level on a pixel-by-pixel basis to remove the reset noise component common to both signals. This operation is called correlated double-sampling (CDS).
One prior art CDS is shown in block diagram form in FIG. 1. This is a pipelined CDS circuit. It has two non-overlapping time phases of operation: In the Q1 phase of the pipelined CDS circuit, the reset level is sampled by sample-and-hold (S/H) #1. A schematic diagram of a typical S/H is shown in FIG. 2. In the Q2 phase, the data level is sampled by S/H #2. Simultaneously, S/H #3 samples the output of S/H #1.
Drawbacks of the pipelined CDS technique are: (1) there are three sampling operations, which increases the noise over techniques requiring only two sampling operations; and (2) any gain or offset mismatch between the reset path (S/H #1 and S/H #3) and the data path (S/H #2) limits the ability of the CDS to remove reset noise.
Another prior art CDS is shown in FIG. 3. This is a dual CDS circuit.
S/H #1 and S/H #2 form a single CDS circuit, and S/H #3 and S/H #4 form a second single CDS circuit. Each single CDS processes alternate pixels. Thus, two CDS circuits are required to process all pixels.
The dual CDS has four phases of operation. In the Q1A phase, the reset level of the first pixel is sampled by S/H #1. The output switch is set to B. In the Q1B phase, the data level of the first pixel is sampled by S/H #2. The output switch is set to B. In the Q2A phase, the reset level of the second pixel is sampled by S/H #3. The output switch is set to A. In the Q2B phase, the data level of the second pixel is sampled by S/H #4. The output switch is set to A.
Compared to the pipeline CDS of FIG. 1, the dual CDS has lower noise because only two sampling operations are performed for each pixel. Also, the AGC has a full period to sample each pixel.
Drawbacks of the dual CDS scheme include: (1) two CDS circuits are required because the previous pixel value must be held while the reset level of the next pixel is sampled; and (2) even and odd pixels use different CDS circuits, causing gain and offset errors which must be removed.